1. Field of the Invention
The present invention relates generally to semiconductor fabrication. More particularly, the present invention relates to methods for making electrical interconnects from one surface of a substrate of a semiconductor component to the opposite surface of the substrate of the semiconductor component and, more particularly, to methods for fabricating a through-via in a wafer, interposer, or other substrate.
2. State of the Art
Semiconductor chips may be produced with integrated circuits on both sides of the chip or may be designed to connect to or interact with other electronic components or other semiconductor chips. Interposers may be utilized for interfacing two electrical components, such as a semiconductor device and a printed circuit board, and contactor boards may be used to interface a semiconductor wafer and a probe card for testing the dice on the semiconductor wafer. Semiconductor chips may be formed of semiconductor wafer or other bulk substrate material, while interposers and contactor boards may be formed of silicon, ceramic or polymeric substrates.
Conductively lined or filled holes (hereinafter “vias”) are used for connecting an integrated circuit on one side of a chip to: an integrated circuit on the other side of the chip, a ground or other bias voltage, another electronic component or an integrated circuit on another chip. Vias are also used for providing electrical communication between structures disposed on opposing sides of an interposer or contactor board, wherein the structures may align with contact pads or other structures of electrical components and establish electrical connection between the various components.
The continued miniaturization of integrated circuits results in vias having increasingly higher aspect ratios, which term refers to the ratio of height or length to width or diameter of the via. One factor contributing to the increasingly higher aspect ratios is that the width of vias is continually getting smaller. Known processes used for filling the high-aspect-ratio vias in stacked chips, interposers and contactor boards, which are typically about fifty microns wide, have difficulty filling these vias without forming voids or keyholes in the via. Conventionally, the vias may be lined with a seed layer of a metal, such as copper, using chemical vapor deposition (CVD) or physical vapor deposition (PVD), whereafter the seed layer is coated by electroplating. As the aspect ratios of the vias get higher, it becomes more difficult to cause the plating material to line or fill the vias without vugs, voids, or keyholes therein, which adversely affect the conductivity of the via.
Referring to FIG. 1, there is shown a cross-section of a substrate generally at 10. The substrate 10 includes a via 12 that is filled using an electroplating process known in the art. The interior of the via 12 is coated with a metal layer 14, which has been deposited using the electroplating process. Electroplating is an electrochemical process by which metal, in ionic form in solution, is deposited on a substrate immersed in a bath containing the ionic form of the metal. A current is passed from an anode through the electroplating solution such that the metal ions are deposited on the cathode provided by a seed layer of metal of the substrate. As illustrated, a surface of the metal layer 14 is uneven and when the via 12 is filled to completion, the uneven surface may result in the formation of one or more voids in the contact mass filling the via 12. In other known processes, the via may be filled by an electroless plating process. In electroless plating, a seed layer may be formed by, for example, using plasma-enhanced chemical vapor deposition (PECVD). The seed layer is coated by a metal layer by placing the substrate in a bath that contains metal ions in aqueous solution and a chemical reducing agent such that the metal ions are deposited on the seed layer by a chemical reduction process.
FIG. 2 illustrates a cross-section of another substrate generally at 20. The substrate 20 includes a via 22 filled with a metal layer 24 using electroplating as known in the art. The metal layer 24 was deposited more efficiently near the upper and lower surfaces of the substrate 20 and resulted in the via 22 being substantially closed near the upper and lower surfaces of the substrate 20 while a middle portion of the via 22 was left unfilled. The unfilled portion 26 of the via 22 is referred to as a “keyhole,” and the presence of the keyhole detracts from the electrical conductivity of the via 22.
In an attempt to avoid the formation of voids and keyholes in the via, other methods have been developed to fill the vias. FIG. 3 is a cross-section of a substrate generally at 30. The substrate 30 includes a via 32, being filled using electroless plating as known in the art. The substrate 30 is placed in a bath for an electroless plating process, also referred to as “immersion plating.” As illustrated, a metal layer 34 is formed over a seed layer (not shown) on the sidewall of the via 32 by the continuous deposition of metal until the via 32 is substantially filled with the metal. However, the electroless deposition process of FIG. 3 may result in voids or depressions being present in the via 32. Further, since electroless plating is relatively slow, i.e., the metal, such as nickel, is deposited at a maximum rate of approximately 20 microns per hour, the extended time to complete the deposition process may be undesirable. For instance, if the via is 70 μm wide, the deposition process would take about one and three-quarter hours to deposit about 35 μm of metal on the interior of the via 32 (70 μm/2) as the metal layer 34 grows inwardly toward the center of the via to completely fill the via 32.
In another attempt to avoid the formation of voids and keyholes in a via, an electroless bottom fill process as known in the art may be used. FIG. 4 illustrates a cross-section of a substrate generally at 40. The substrate 40 includes a via 42 and a layer of a metal 44 deposited on a bottom 46 of the via 42 and growing towards a top 48 of the via 42. The bottom 46 of the via 42 may comprise a suitable metal such as copper (Cu), nickel (Ni) or tungsten (W). The approach of the bottom fill process is that by depositing the layer of metal 44 in one direction, upward, and not from the sides of the via 42 (as shown in FIG. 3), voids and keyholes are not formed between layers of metal growing towards each other. The bottom fill process may be performed with copper in an attempt to avoid keyhole formation in the via due to migration of the copper. However, since the vias may be as deep as, e.g., 700 microns, and electroless plating deposits metal at the aforementioned relatively slow rate, the process to completely fill the via is unacceptably time-consuming. Electroplating from the bottom of a via is also known, wherein a conductor serving as a cathode is placed over the bottom of a substrate, covering the bottoms of the vias. However, such an approach severely limits the stage of wafer processing at which the via may be filled and may impose design limitations on other structures formed or to be formed on the substrate.
Accordingly, a need exists for an improved method for filling vias that is faster than known processes, does not leave voids, depressions, or keyholes in the filled via and is cost effective to manufacture.